D Flip Flop or a Delay Flip Flop has only data input D and two outputs which are complementary to each other and are denoted by Q and Q’. The Q output is identical to the D input except with one pulse time delay, hence the name D Flip Flop. D flip flop is used to avoid the forbidden state of S-R Latch. Since the inputs to the cross coupled NAND gates (gate 3 & 4) are always in opposite states, the invalid state (forbidden state) never occurs.
Let Qn and Qn+1 denote the present state and next state of the flip flop, here is the truth table and circuit diagram of a D Flip Flop
It is used in applications where delay is required.