# J-K Flip Flop In Digital Electronics

This is Part 4 in a series on Flip Flops in Digital Electronics. The full series is Part 1, Part 2, Part 3, Part 4, Part 5 and Part 6.

The J-K Flip Flop has two data inputs J & K, a single clock input and two outputs Q and Q’.  J-K Flip Flop is used to avoid the forbidden state of S-R Flip Flop.

Let Qn and Qn+1 represent the present state and next state of the flip flop, here is the truth table and circuit diagram of a J-K Flip Flop

 J K Qn Qn’ Qn+1 State 0 0 0 1 Qn Hold 0 0 1 0 Qn Hold 0 1 0 1 Qn 0 0 1 1 0 0 - 1 0 0 1 1 - 1 0 1 0 Qn 1 1 1 0 1 1 - 1 1 1 0 0 -

When J=1, K=1, the Q output will be in the Qn’ state after clocking i.e. Qn+1=Qn’. This is known as toggling. The flip flop will complement itself each time the circuit switches from high to low. The flip flop is said to toggle.

Race-Around Condition In J-K Flip Flop

Practically, we don’t get toggling. Since, clock pulse is more than the propagation delay, so within one clock pulse the output will keep on toggling again and again and it may become indeterminate. This is known as race around condition. Race Around condition occurs because of the feedback connection.

There are three ways to avoid Race-Around Condition:

1. If Ton < Tpd

i.e. clock pulse is less than the propagation delay. Practically Tpd is of the order of nanoseconds or picoseconds and therefore, it is only a theoretical possibility to get clock pulse lower than propagation delay.

2. Another way is by using Edge Triggering

In edge triggering output is affected only at the time of presence of edge i.e. only during the rising or falling edge of a clock pulse. When the input clock pulse makes a +ve going transition (or a -ve going transition), the value of input is transferred to output i.e. Q. Changes in input when clock is maintained at a steady 1 value do not affect Q. Moreover, a -ve pulse transition does not affect the output and nor does when clock pulse is 0. Hence the edge triggered flip flop eliminates any feedback problem in sequential circuit.

3. By using Master-Slave Flip Flop

Read the full series at Part 1, Part 2, Part 3, Part 4, Part 5 and Part 6.

1. You are using the term “flip flop” interchangeably with that of “latch” where both are different.
The difference between latches and flip-flops is that for latches, their outputs are constantly affected by their inputs as long as the enable signal is asserted. In other words, when they are enabled, their content
changes immediately when their inputs change. Flip-flops, on the other hand, have their content change only either at the rising or falling edge of the enable signal. This enable signal is usually the controlling clock signal. After the rising or falling edge of the clock, the flip-flop content remains constant even if the input changes.

First you are referring to the “JK Flip Flop” and then also saying that the value of the flip flop will keep toggling within one clock pulse. This is against the very definition of flip flop as flip flops are edge sensitive ONLY. It’s the very definition of flip flop. SO, the race around condition you have mentioned here cannot be applicable to a “flip flop” in the first place. On the other hand, a latch doesn’t have clocks associated with it. It is not a synchronous circuit. So, your explanation is totally incorrect and misleading.

• There are two types of triggering in flip flops, one is level triggering and another is edge triggering.so race around conditions occur in jk flip flop when level triggering is used and that’s why there is the solution for them is using edge triggering.