The J-K Flip Flop has two data inputs J & K, a single clock input and two outputs Q and Q’. J-K Flip Flop is used to avoid the forbidden state of S-R Flip Flop.
Let Qn and Qn+1 represent the present state and next state of the flip flop, here is the truth table and circuit diagram of a J-K Flip Flop
When J=1, K=1, the Q output will be in the Qn’ state after clocking i.e. Qn+1=Qn’. This is known as toggling. The flip flop will complement itself each time the circuit switches from high to low. The flip flop is said to toggle.
Race-Around Condition In J-K Flip Flop
Practically, we don’t get toggling. Since, clock pulse is more than the propagation delay, so within one clock pulse the output will keep on toggling again and again and it may become indeterminate. This is known as race around condition. Race Around condition occurs because of the feedback connection.
There are three ways to avoid Race-Around Condition:
1. If Ton < Tpd
i.e. clock pulse is less than the propagation delay. Practically Tpd is of the order of nanoseconds or picoseconds and therefore, it is only a theoretical possibility to get clock pulse lower than propagation delay.
2. Another way is by using Edge Triggering
In edge triggering output is affected only at the time of presence of edge i.e. only during the rising or falling edge of a clock pulse. When the input clock pulse makes a +ve going transition (or a -ve going transition), the value of input is transferred to output i.e. Q. Changes in input when clock is maintained at a steady 1 value do not affect Q. Moreover, a -ve pulse transition does not affect the output and nor does when clock pulse is 0. Hence the edge triggered flip flop eliminates any feedback problem in sequential circuit.
3. By using Master-Slave Flip Flop