Master-Slave Flip Flop In Digital Electronics

This is Part 5 in a series on Flip Flops in Digital Electronics. The full series is Part 1, Part 2, Part 3, Part 4, Part 5 and Part 6.

The circuit of Master-Slave Flip Flop is basically two latches connected serially. The first latch is called the Master and the second is termed Slave. In a Master-Slave Flip Flop inputs are fed at the +ve edge and output is available at the -ve edge.

Let Qn and Qn+1 represent the present state and next state of the flip flop, here is the truth table and circuit diagram of a Master-Slave Flip Flop:

 CLK J K Qn+1 Qn+1’ 1 0 0 Qn Qn’ 1 0 1 0 1 1 1 0 1 0 1 1 1 Qn’ Qn

Clock is connected directly to Master and inverted to Slave. When clock is high – Master is functional and when clock is low – Slave is functional. Q and Q’ will be same as QM and QM’. Thus, what a master latch does when the clock goes high, the slave latch copies when the clock goes low.

For example, when J=1, K=1, let Qn=0 and Qn’=1. When clock is high then Qn+1=QM=1, QM’=0. When clock is low then Q=QM=1, Q’=QM’=0. Thus, even when J=1,K=1, the outputs are complement to each other.

Read the full series at Part 1, Part 2, Part 3, Part 4, Part 5 and Part 6.

1. how i wish you indicated the timing diagram of the master slave/pulse triggered…………….. i mean the out put wave forms

2. explain briefly about glitches in counting sequence in asyncronous and syncronous counter………….
plz. mail me in pdf.

3. Please explain this All portion of the master slave jk ff clear and full understandable okay

4. When the clock is LOW , the outputs from the master flip flop are latched and any additional changes to its inputs are ignored. The gated slave flip flop now responds to the state of its inputs passed over by the master section.

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