Shift Registers In Digital Electronics

There are couple of ways to define a Register used in Digital Electronics.

“Registers are data storage devices that are more sophisticated than latches.”

“A register is a group of binary cells suitable for holding binary information.”

“A group of cascaded flip flops used to store related bits of information is known as a register.”

Application of Registers

These are used in computers for

  • Temporary storage
  • Data transferring
  • Data manipulation
  • As counters

Shift Register

A register that is used to assemble and store information arriving from a serial source is called a shift register. Each flip flop output of a shift register is a connected to the input of the following flip flop and a common clock pulse is applied to all flip flops, clocking them synchronously. Hence the shift register is a synchronous sequential circuit. An n-bit shift register consists of n Flip Flops and the gates control the shift operation.

There are four types of Shift Registers:

  1. Serial-In, Serial-Out (SISO)
  2. Parallel-In, Serial-Out (PISO)
  3. Serial-In, Parallel-Out (SIPO)
  4. Parallel-In, Parallel-Out (PIPO)

 

Serial-In, Serial-Out (SISO)

Serial-In, Serial-Out shift register can be constructed by using D flip flops. This type of shift register accepts data serially i.e. one bit at a time and produces stored information on its output serially.

Here, four flip flops are cascaded. Since each flip flop can store only one bit, the register can store maximum four bits. More flip flops can be cascaded to store more than 4 bits. Clock is applied simultaneously to all flip flops clocking them synchronously.

We know that in a D Flip Flop, the Q output is identical to the D input except with one pulse time delay. Therefore, there will be a delay i.e. it will take one clock pulse to transfer the bit to next flip flop.

Let’s understand Shifting by taking an example. Let say the 4-bits applied to serial input are 1010. Here LSB 0 is applied first and MSB 1 is applied last since the input is applied in serial fashion.

Now, refer the table below. At first clock pulse, i.e. when CLK = 1, LSB 0 is applied to Serial In.

At CLK = 2, next bit i.e. 1 is applied to Serial In. At this moment, 0 applied at CLK=1, shifts to Qa.

At CLK = 3, next bit i.e. 0 is applied to Serial In. At this moment , 1 applied at CLK = 2 shifts to Qa and o applied at CLK = 1 shifts to Qb.

And so on. For shifting out, 0′s are applied at Serial In.

CLK Da / Serial In Qa Qb Qc Qd / Serial Out
0 0 0 0 0 0
1 0 0 0 0 0
2 1 0 0 0 0
3 0 1 0 0 0
4 1 0 1 0 0
5 0 1 0 1 0
6 0 0 1 0 1
7 0 0 0 1 0
8 0 0 0 0 1
9 0 0 0 0 0

It will require 4 clock pulses for Shifting In the data and 4 clock pulses for Shifting Out the data. Thus, for an n-bit SISO shift register, 2n clock pulses are required.

Serial-In, Parallel-Out (SIPO)

Serial-In, Parallel-Out shift register can be constructed by using D flip flops. This type of shift register accepts data serially i.e. one bit at a time and produces stored information on its output parallely i.e. all the outputs are available simultaneously.

Here, four flip flops are cascaded. Since each flip flop can store only one bit, the register can store maximum four bits. More flip flops can be cascaded to store more than 4 bits. Clock is applied simultaneously to all flip flops clocking them synchronously.

We know that in a D Flip Flop, the Q output is identical to the D input except with one pulse time delay. Therefore, there will be a delay i.e. it will take one clock pulse to transfer the bit to next flip flop. All the outputs are available simultaneously at Qa, Qb, Qc and Qd.

Note: Circuit diagram of SIPO is same as SISO except that outputs are available simultaneously rather than serially at Serial Out.

Parallel-In, Serial-Out (PISO)

Parallel-In shift register can be constructed by using D flip flops. This type of shift register accepts data parallely i.e. all the bits are input simultaneously.

 

  • Serial In is kept at 0.
  • For shifting in the data parallely i.e. all the bits are fed simultaneously, LOAD=1. Whatever is available at a3 will be applied to Preset input of flip flop. Thus, the flip flop is set or reset based on the Preset input and this is how all the input bits are applied in parallel.
  • After shifting the data in, LOAD=0 and output is obtained from Serial Out.

The data will be available at the output after 4 clock pulse.

Parallel-In, Parallel-Out (PIPO)

Parallel-In shift register can be constructed by using D flip flops. This type of shift register accepts data parallely i.e. all the bits are input simultaneously and produces stored information on its output parallely i.e. all the outputs are available simultaneously.

  • Serial In is kept at 0.
  • For shifting in the data parallely i.e. all the bits are fed simultaneously, LOAD=1. Whatever is available at a3 will be applied to Preset input of flip flop. Thus, the flip flop is set or reset based on the Preset input and this is how all the input bits are applied in parallel.
  • After shifting the data in, LOAD=0 and output is obtained from Parallel Outputs Qa, Qb, Qc and Qd.

No clock pulse is required. Data can be shifted into or out of the register in parallel.

Note: Circuit diagram of PIPO is same as PISO except that outputs are available simultaneously rather than serially at Serial Out.

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